T1W-MISManufacturing

Factory cell layout / machine placement

Place machines/cells so adjacency conflicts are avoided — geometric, weighted by throughput value.

Sector

Manufacturing

Likely buyer

Manufacturers; industrial engineers

Hardware gate

Unweighted today; weighted → Vela

Taxonomy

throughput-limited × accelerating

Ω 9.4 · δ ±12.6 rad/µs · 4000 ns · R_b 9.1 µm

Machine cells conflict when adjacency is unsafe/inefficient; atom size = throughput value.

Weighted instance: site values map to per-atom detuning — on hardware this needs Vela-class local addressing. Emulated exactly here.

GTM talk track

'Your plant floor is a conflict graph — machines that can't sit next to each other. That's MIS.'

OGSM — product operating frame

Objective

Prove layout optimization on a real line.

Goals

Strategies

Measures

Horizon	Outcome we create	Buyer behavior change	Result we measure
Now	Plant sees a layout on sample line	Prospect runs the emulated demo on their own instance data	Booked QPU-time evaluation or paid pilot
Next	Plant benchmarks a full floor	Prospect co-designs a scoped benchmark against their incumbent solver	Documented crossover curve; expansion to production instances
Later	Plant adopts for redesign	Prospect standardizes on the workflow or buys an on-prem system	Recurring QPU consumption / system sale; reference case

Fit notes (honesty gate)

Adjacency conflicts are geometric; native.

Ready to run this on real hardware?

Emulation-verified today — the same program runs on a Pasqal QPU unchanged.