T2UD-MISAdvanced MaterialsManufacturing
Semiconductor mask / layout conflict deconfliction
Resolve geometric design-rule conflicts in chip layout — geometric constraint satisfaction; high-value, contested.
Sector
Semiconductor EDA
Likely buyer
Fabless designers; EDA vendors
Hardware gate
Orion; large layouts → scale
Taxonomy
throughput-limited × accelerating
Live demo — adiabatic sweep on 5 features
Ω 9.4 · δ ±12.6 rad/µs · 4000 ns · R_b 9.1 µmLayout features conflict when spacing rules are violated; find the largest rule-clean set.
GTM talk track
'Design-rule conflicts are geometric exclusion constraints — the native shape.'
OGSM — product operating frame
Objective
Scope a geometric DRC subproblem.
Goals
- One designer runs a layout block
Strategies
- Map DRC conflicts to geometry
Measures
- Conflicts resolved
OBR — outcome-based roadmap
| Horizon | Outcome we create | Buyer behavior change | Result we measure |
|---|---|---|---|
| Now | Designer sees a block deconflicted | Prospect runs the emulated demo on their own instance data | Booked QPU-time evaluation or paid pilot |
| Next | Designer benchmarks a macro | Prospect co-designs a scoped benchmark against their incumbent solver | Documented crossover curve; expansion to production instances |
| Later | Designer integrates into flow | Prospect standardizes on the workflow or buys an on-prem system | Recurring QPU consumption / system sale; reference case |
Fit notes (honesty gate)
Expanded-domain: DRC-adjacent geometric constraints; high value, contested by EDA incumbents.
Ready to run this on real hardware?
Emulation-verified today — the same program runs on a Pasqal QPU unchanged.